1. Field of the Invention
This invention relates to a method and circuit for detection of solder joint failures in digital electronic packages such as Field Programmable Gate Arrays (FPGAs) and Microcontrollers and between the packages's ball grid array (BGA) and printed wire board (PWB).
2. Description of the Related Art
Solder-joint connections from digital electronic packages such as FPGAs or Microcontrollers to Printed Wire Boards (PWB) are a major reliability problem. Modern Ball Grid Array (BGA) packages have several thousand pins and the number of pins on these packages is likely to increase over the next several years. The increased number of pins on the packages is necessary to support the evolving complexity of circuits; however, one of the drawbacks of the increase is reduced reliability. For many applications it would be useful to detect failures or precursors to failures in the solder-joint connections from inside the digital logic on the die, through the multiple internal interconnects inside the package and through the external interconnects to circuitry on the PWB; together the “solder joint network”.
Failure mechanisms include manufacturing defects and operation of the electronic package. Manufacturing defects may include variance in the materials, variance in the manufacturing process or assembly of one specific package. These types of defects will produce a high probability of failure early in the expected life cycle of a part. Operation of the package subjects solder joints to physical stress/strain, thermal stress/strain, voltage stresses, shock, vibration and electro-migration. These stresses will typically produce random failures at a fairly low rate during the useful life of the period; then near the end of the expected life cycle the failure rate will increase due to accumulated fatigue of the solder joints.
As shown in FIG. 1a, an exemplary FPGA 10 includes at least one flip-chip 12 consisting of a die mount 18 and die 16 mounted inside a cavity 14 of a BGA package 22. Electrical components such as transistors, diodes and capacitors that are configured via wire interconnects on a die 16 together constitute the FPGA. The FPGA includes write logic that is connected through an output buffer to a pad on the die. Similarly an input buffer is connected from a pad to read logic. The buffers may be either inverting or non-inverting. Flip-chip 12 is placed inside BGA package 22 so that the solder balls 20 (also called solder bumps) inside the BGA package 22 touch pads, lands or vias of flip-chip 12 and they are soldered to form solder-joint connections. Vias lead from contacts (not shown) of solder bumps 20 to an outside ball limiting metallurgy (BLM) 24 and primary BGA solder balls 26 to complete the FPGA 10. In FIG. 1b, some manufacturing processes result in an intervening connection between die connection 40 and a flip-chip connection 42, and sometimes die connection 40 and flip-chip connection 42 are one and the same: a single connection. The FPGA is placed so that primary BGA solder balls 26 contact solder paste on metal LANDs 28 on a PWB 30. The assembled PWB is heated and the solder balls 26 melt and reflow to attach themselves to the metal LAND. The PWB is configured so that the metal LANDs are connected by vias and/or wiring 32 to one or more I/O nodes 34 for external circuitry on the PWB.
As shown in FIGS. 1b and 1c, a “solder joint network” 36 that connects the output of the write logic (or the input of read logic) on die 16 to node 34 on the PWB consists of considerably more than just the primary BGA 26 between the package and the PWB. As shown in FIG. 1b, a simplified mechanical representation of the network includes buffer connection 38, die connection 40 (first BGA, pads, vias . . . ), flip-chip connection 42 (second BGA, pads, vias . . . ), package connection 44 (primary BGA, BLM, pads, vias . . . ) and the PWB connection 46. As shown in FIG. 1c, the electrical representation of the network includes resistances for the connections (buffer, die, flip chip, package and PWB) and the interconnections 47a-47d between connection nodes for each of the mechanical components. There is a contact resistance on each side of a solder-ball connection plus a connection resistance called a contact resistance. The specific resistances are as follows:
R38LC=left-side contact resistance of solder ball 38
R38=resistance of solder ball 38
R38RC=right-side contact resistance of solder ball 38
R38_40=resistance of interconnection between contacts of solder balls 38 and 40
R40LC=left-side contact resistance of solder ball 40
R40=resistance of solder ball 40
R40RC=right-side contact resistance of solder ball 40
R40_42=resistance of interconnection between contacts of solder balls 40 and 42
R42LC=left-side contact resistance of solder ball 42
R42=resistance of solder ball 42
R42RC=right-side contact resistance of solder ball 42
R42_44=resistance of interconnection between contacts of solder balls 42 and 44
R44LC=left-side contact resistance of solder ball 44
R44=resistance of solder ball 44
R44RC=right-side contact resistance of solder ball 44
R44_46=resistance of interconnection between contacts of solder balls 44 and 46
R46LC=left-side contact resistance of solder ball 46
R46=resistance of solder ball 46
R446C=right-side contact resistance of solder ball 46
The secondary connections in FIG. 1c are shown as small solder balls, but might be comprised of a combination of solder balls, wire bonds and integrated circuit vias and pads. If each connection and interconnection in the network is sound, each resistance will be low and the total network resistance will be low.
The manufacturing defects and operational failure mechanisms will typically manifest as voids, cracks or corrosion in the solder balls 26, cracks, corrosion or diffusion in the ball limiting metal (BLM) 24 between each ball and the package or migration between the balls 26. Although failures typically occur at the interface of a BLM and its attached ball or at the interface of a PWB LAND and its attached ball, the same failure mechanisms might cause solder joint failures within the package itself at any of the connections. Any such failure will result in a defective electronic package.
Many studies have been conducted to determine the reliability of BGA packages. They conclude that solder-joint networks fail intermittently and as hard failures. An intermittent failure manifests itself during thermal or mechanical transients or disturbances in the form of short-duration high-resistance spikes. The second type of solder-joint failure is a hard failure, which manifests itself as a steady-state high-impedance, including an open of infinite impedance. Intermittent failures typically precede hard failures; they therefore represent the most relevant breakdown mechanism for solder joint failures. The tests also indicate that, prior to hard failure of the BGA package, one or more solder joints exhibit changes in resistance on the order of hundreds of milliohms and ohms, which do not result in a hard failure.
To evaluate the failure mechanisms that affect solder bump reliability and to evaluate the efficacy of manufacturing materials and processes, sample devices are subjected to a number of tests including moisture resistance test, bump shear/pull test, temperature cycle life test and high temperature operation and storage tests. These tests can be used to evaluate a particular design; what is the expected useful life, what are the likely failures, etc. or to gain data to improve upon the design. The tests can also be used to evaluate a batch of devices for manufacturing defects. If a number of devices fail initially or early on then there may be something wrong with the materials or process control. None of these tests are suitable for testing actual fielded devices during operation.
The effects of these tests on the solder joints can be evaluated using a variety of techniques. Methods of analyzing the solder joints without opening the package include radiography, ultrasonic examination and hermetic evaluation. Alternately, the package can be opened, cut or shaved to expose to the solder joints for visual or other inspection. Finally, as shown in FIG. 2, the integrity of the solder joint can be evaluated by measuring the bump connection resistance of a BGA package 50 flip-chip mounted to a PWB 52 during the test and judging defects by the degree of change in the connection resistance.
As shown in FIG. 2, wire segments 54 connect vias 56 inside the package and PWB wiring 58 connects pads 60 on the PWB to connect solder bumps 62 attached to ball-limiting metallurgy 66 from the primary BGA in a “daisy chain”. A meter 64 directly measures the resistance for all bumps 62 at the same time by either applying a voltage and measuring a current or vice-versa. Alternately, the wire segments and PWB can be configured to measure the resistance between two bumps 62 at a time, so increases in resistance due to cracking can be monitored.
The techniques for direct measurement of the solder-joint resistance have a number of limitations. The BGA package and PWB are ‘blanks’ or ‘dummies’ configured for the 4-wire or continuous measurements, and therefore they are not the same as the operational devices. Specifically, the package does not include the FPGA flip-chip containing the operational logic gates and buffers: Digital logic gates within the solder joint network prevent the direct measurement of the network resistance because those logical devices and buffers present an open circuit (infinite impedance) to series direct measurement techniques. It follows that these tests cannot be performed on actual operational devices, either in the lab or particularly in the field. Finally, there are several instruments available to perform these measurements, however, besides being bulky and suitable for lab testing, these instruments cannot be used to perform real-time, in-use testing of fielded, operational FPGA BCA solder joint networks.
The current test procedures for measuring the resistance may be adequate for evaluating the condition of the solder joints formed by the primary BGA during or after the various stress tests to evaluate the design or potential manufacturing defects, but they are not applicable to actual operational devices, particularly for ongoing testing during the normal operation of a fielded device. Furthermore, these tests are not capable of evaluating the internal solder-joint connections of the FPGA BGA package or the flip-chip prior to subsequent assembly and fielding of the device. There remains a need for a capability to measure the resistance of the solder-joint network for screening devices during different stages of assembly and particularly during normal operation of the fielded device.